View MAX3681_84179.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-1091; Rev 0; 6/96
K ATION EVALU BLE AVAILA
IT
+3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS Outputs
______________________________Features
o Single +3.3V Supply o 622Mbps Serial to 155Mbps Parallel Conversion o 265mW Power o LVDS Data Outputs and Synchronization Inputs o Synchronization Input for Data Realignment and Reframing o Differential 3.3V PECL Clock and Data Inputs
_________________General Description
The MAX3681 deserializer is ideal for converting 622Mbps serial data to 4-bit-wide, 155Mbps parallel data in ATM and SDH/SONET applications. Operating from a single +3.3V supply, this device accepts PECL serial clock and data inputs, and delivers low-voltage differential-signal (LVDS) clock and data outputs for interfacing with high-speed digital circuitry. It also provides an LVDS synchronization input that enables data realignment and reframing. The MAX3681 is available in the extended-industrial temperature range (-40C to +85C), in a 24-pin SSOP package.
MAX3681
__________________________Applications
622Mbps SDH/SONET Transmission Systems 622Mbps ATM/SONET Access Nodes Add/Drop Multiplexers Digital Cross Connects
________________Ordering Information
PART MAX3681EAG TEMP. RANGE -40C to +85C PIN-PACKAGE 24 SSOP
Pin Configuration appears at end of data sheet.
___________________________________________________________________T ypical Operating Circuit
VCC = +3.3V VCC VCC = +3.3V VCC = +3.3V 130 PHOTODIODE 130 SD+ PD3+ 100*
MAX3681
PD3PD2+ 100*
MAX3675
82 LIMITING AMP DATA AND CLOCK RECOVERY 130 82
PD2PD1+ 100* PD1OVERHEAD TERMINATION
SD-
PREAMP
100
VCC = +3.3V
PD0+ 100* 130 SCLK+ SCLKPCLKPD0PCLK+ 100*
MAX3664
82
82 SYNC+
*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION. THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50.
GND
SYNC-
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
+3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS Outputs MAX3681
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND) VCC ...........................................................................-0.5V to 5V PECL Inputs (SD+/-, SCLK+/-).................................VCC + 0.5V LVDS Inputs (SYNC+/-)............................................VCC + 0.5V Output Current, LVDS Outputs (PCLK+/-, PD_+/-) .............10mA Continuous Power Dissipation (TA = +85C) SSOP (derate 8.00mW/C above +85C) ......................520mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +160C Lead Temperature (soldering, 10sec) .............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential loads = 100, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C.) PARAMETER Supply Current PECL INPUTS (SD+/-, SCLK+/-) Input High Voltage Input Low Voltage Input High Current Input Low Current Input Voltage Range Differential Input Threshold Threshold Hysteresis Differential Input Resistance Output High Voltage Output Low Voltage Differential Output Voltage Change in Magnitude of Differential Output Voltage for Complementary States Output Offset Voltage Change in Magnitude of Output Offset Voltage for Complementary States Single-Ended Output Resistance Change in Magnitude of SingleEnded Output Resistance for Complementary States VIH VIL IIH IIL VI VIDTH VHYST RIN VOH VOL VOD VOD VOS VOS RO RO 40 70 1 TA = +25C 1.125 0.925 250 400 25 1.275 25 140 10 85 VIN = VIH(MAX) VIN = VIL(MAX) Differential input voltage = 100mV Common-mode voltage = 50mV VCC - 1.16 VCC - 1.81 -10 -10 0 -100 70 100 115 1.475 VCC - 0.88 VCC - 1.48 10 10 2.4 100 V V A A V mV mV V V mV mV V mV % SYMBOL ICC CONDITIONS MIN 55 TYP 80 MAX 120 UNITS mA
LVDS INPUTS AND OUTPUTS (SYNC+/-, PCLK+/-, PD_+/-)
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, differential loads = 100, TA = +25C, unless otherwise noted.) (Note 1) PARAMETER Maximum Serial Clock Frequency Serial Data Setup Time Serial Data Hold Time Parallel Clock to Data Output Delay SYMBOL fSCLK tSU tH tCLK-Q CONDITIONS MIN 622 800 50 200 550 900 TYP MAX UNITS MHz ps ps ps
Note 1: AC Characteristics guaranteed by design and characterization. 2 _______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS Outputs
__________________________________________Typical Operating Characteristics
(VCC = +3.0V to +3.6V, differential loads = 100, unless otherwise noted.)
MAXIMUM SERIAL CLOCK FREQUENCY vs. TEMPERATURE
MAX3681-01
MAX3681
SERIAL DATA-SETUP TIME vs. TEMPERATURE
MAX3681-03
SERIAL DATA-HOLD TIME vs. TEMPERATURE
MAX3681-04
2.0 MAX SERIAL CLOCK FREQUENCY (GHz) 1.8 VCC = 3.6V 1.6 1.4 VCC = 3.0V
400 SERIAL DATA-SETUP TIME (ps) 360
-100 SERIAL DATA-HOLD TIME (ps) -140
320 280
-180 -220
1.2
240
-260
1.0 -50 -25 0 25 50 75 100 TEMPERATURE (C)
200 -50 -25 0 25 50 75 100 TEMPERATURE (C)
-300 -50 -25 0 25 50 75 100 TEMPERATURE (C)
SUPPLY CURRENT vs. TEMPERATURE
MAX3681-02
PARALLEL CLOCK TO DATA OUTPUT PROPAGATION DELAY vs. TEMPERATURE
MAX3681-05
120
700 PARALLEL CLOCK TO DATA PROPAGATION DELAY (ps) 650
SUPPLY CURRENT (mA)
100
VCC = +3.6V VCC = +3.3V
600 550
80 VCC = +3.0V 60
500
40 -50 -25 0 25 50 75 100 TEMPERATURE (C)
450 -50 -25 0 25 50 75 100 TEMPERATURE (C)
_______________________________________________________________________________________
3
+3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS Outputs MAX3681
______________________________________________________________Pin Description
PIN 1, 2, 5, 8, 12 3 4 6 7 9, 15, 22 10 11 13 14 16, 18, 20, 23 17, 19, 21, 24 NAME VCC SD+ SDSCLK+ SCLKGND SYNC+ SYNCPCLKPCLK+ PD0- to PD3PD0+ to PD3+ +3.3V Supply Voltage Noninverting PECL Serial Data Input. Data is clocked on the SCLK signal's positive transition. Inverting PECL Serial Data Input. Data is clocked on the SCLK signal's positive transition. Noninverting PECL Serial Clock Input Inverting PECL Serial Clock Input Ground Noninverting LVDS Synchronizing Pulse Input. Pulse the SYNC signal high for at least two SCLK periods to shift the data alignment by dropping one bit. Inverting LVDS Synchronizing Pulse Input. Pulse the SYNC signal high for at least two SCLK periods to shift the data alignment by dropping one bit. Inverting LVDS Parallel Clock Output Noninverting LVDS Parallel Clock Output Inverting LVDS Parallel Data Outputs. Data is updated on the positive transition of the PCLK signal. See Figure 2 for the relationship between serial-data-bit position and output-data-bit assignment. Noninverting LVDS Parallel Data Outputs. Data is updated on the positive transition of the PCLK signal. See Figure 2 for the relationship between serial-data-bit position and output-data-bit assignment. FUNCTION
_______________Detailed Description
The MAX3681 deserializer uses a 4-bit shift register, 4-bit parallel output register, 2-bit counter, PECL input buffers, and low-voltage differential-signal (LVDS) input/output buffers to convert 622Mbps serial data to 4-bit-wide, 155Mbps parallel data (Figure 1). The input shift register continuously clocks incoming data on the positive transition of the serial clock (SCLK) input signal. The 2-bit counter generates a parallel output clock (PCLK) by dividing down the serial clock frequency. The PCLK signal is used to clock the parallel output register. During normal operation, the counter divides the SCLK frequency by four, causing the output register to latch every four bits of incoming serial data. The synchronization inputs (SYNC+, SYNC-) are used for data realignment and reframing. When the SYNC signal is pulsed high for at least two SCLK cycles, the parallel output data is delayed by one SCLK cycle. This realignment is guaranteed to occur within two PCLK cycles of the SYNC signal's positive transition. As a result, the first incoming bit of data during that PCLK cycle is dropped, shifting the alignment between PCLK and data by one bit. See Figure 2 for the functional timing diagram and Figure 3 for the timing parameters diagram.
SD+ SDSCLK+ SCLKPECL PECL 4-BIT SHIFT REGISTER 4-BIT PARALLEL OUTPUT REGISTER LVDS PD3+ PD3PD2+ LVDS PD2PD1+ LVDS
MAX3681
PD1PD0+
LVDS
PD0PCLK+
SYNC+ SYNC100 LVDS
2-BIT COUNTER
LVDS
PCLK-
Figure 1. Functional Diagram
4
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS Outputs MAX3681
SCLK
SD
D1-
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
SYNC
PCLK
PD3
D4-
D0
D5
PD2
D3-
D1
D6
PD1
D2-
D2
D7
PD0
D1-
D3
D8
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 2. Functional Timing Diagram
tSCLK = 1 / fSCLK SCLK tSU SD tH
PCLK tCLK-Q PD0-PD3
NOTE: SIGNALS SHOWN ARE DIFFERENTIAL. FOR EXAMPLE, SCLK = (SCLK+) - (SCLK-).
Figure 3. Timing Parameters
_______________________________________________________________________________________
5
+3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS Outputs MAX3681
Low-Voltage Differential-Signal (LVDS) Inputs and Outputs
The MAX3681 features LVDS inputs and outputs for interfacing with high-speed digital circuitry. The LVDS standard is based on the IEEE 1596.3 LVDS specification. This technology uses 250mVp-p to 400mVp-p, differential low-voltage swings to achieve fast transition times, minimized power dissipation, and noise immunity. The parallel clock and data LVDS outputs (PCLK+, PCLK-, PD_+, PD_-) require 100 differential DC termination between the inverting and noninverting outputs for proper operation. Do not terminate these outputs to ground. The synchronization LVDS inputs (SYNC+, SYNC-) are internally terminated with 100 of differential input resistance, and therefore do not require external termination.
+3.3V 130 ZO = 50 130 THEVENIN-EQUIVALENT TERMINATION
MAX3681
PECL INPUTS
ZO = 50
82
82
ECL AC-COUPLING TERMINATION +3.3V 1.6k ZO = 50 1.6k
PECL Inputs
The serial data and clock PECL inputs (SD+, SD-, SCLK+, SCLK-) require 50 termination to (VCC - 2V) when interfacing with a PECL source (see the Alternative PECL Input Termination section).
MAX3681
50 PECL INPUTS
__________Applications Information
Alternative PECL Input Termination
Figure 4 shows alternative PECL input-termination methods. Use Thevenin-equivalent termination when a (VCC - 2V) termination voltage is not available. If AC coupling is necessary, such as when interfacing with an ECL-output device, use the ECL AC-coupling termination.
ZO = 50
-2V
50 2.7k -2V 2.7k
Figure 4. Alternative PECL Input Termination
Layout Techniques
For best performance, use good high-frequency layout techniques. Filter voltage supplies and keep ground connections short. Use multiple vias where possible. Also, use controlled impedance transmission lines to interface with the MAX3681 data inputs and outputs.
6
_______________________________________________________________________________________
+3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS Outputs
__________________Pin Configuration
TOP VIEW
VCC 1 VCC 2 SD+ 3 SD- 4 VCC 5 SCLK+ 6 SCLK- 7 VCC 8 24 PD3+ 23 PD322 GND 21 PD2+
___________________Chip Information
TRANSISTOR COUNT: 724
MAX3681
MAX3681
20 PD219 PD1+ 18 PD117 PD0+ 16 PD015 GND 14 PCLK+ 13 PCLK-
GND 9 SYNC+ 10 SYNC- 11 VCC 12
SSOP
_______________________________________________________________________________________
7
+3.3V, 622Mbps, SDH/SONET 1:4 Deserializer with LVDS Outputs MAX3681
________________________________________________________Package Information
DIM A A1 B C D E e H L INCHES MILLIMETERS MAX MIN MIN MAX 0.078 0.068 1.73 1.99 0.008 0.002 0.05 0.21 0.015 0.010 0.25 0.38 0.008 0.004 0.09 0.20 SEE VARIATIONS 0.209 0.205 5.20 5.38 0.0256 BSC 0.65 BSC 0.311 0.301 7.65 7.90 0.037 0.025 0.63 0.95 8 0 0 8 INCHES MILLIMETERS MAX MIN MAX MIN 6.33 0.239 0.249 6.07 6.33 0.239 0.249 6.07 7.33 0.278 0.289 7.07 8.33 0.317 0.328 8.07 0.397 0.407 10.07 10.33
21-0056A
E
H
C
L
DIM PINS
e
A B D
A1
SSOP SHRINK SMALL-OUTLINE PACKAGE
D D D D D
14 16 20 24 28
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
8 ___________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX3681

	To Download MAX3681 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .